1. Field of the Invention
This invention relates generally to clock dividers and, in particular, to clock dividers using state machines.
2. Description of the Related Art
It is sometimes desirable to divide a clock signal. In particular, it is at times, desirable to divide a clock signal by a non-integer multiple. For example, it may be desirable to obtain an output clock signal that has a period Tout that is 1.5, 2.5 or some other non-integer multiple of Tin, the period of the input clock signal.
Earlier systems use phase lock loops (PLL) to achieve such non-integer multiples of the input clock signal. Use of PLL""s to achieve non-integer clock divide suffers from several disadvantages. First, the PLL circuit occupies a relatively large die area. Second, because PLL involves feedback, it is very sensitive to design parameters. Third, the PLL circuit typically requires a lot of tuning to ensure that it provides the desired non-integer divide. Fourth, the PLL circuit is very difficult to design, in part because it is an active circuit.
As a result, there has been a need for a non-integer clock divider that deals with the above-mentioned shortcomings of the earlier systems.
A clock divider is described. The clock divider includes: a positive edge triggered state machine having a first input for receiving a first input signal and a first output for providing a first output signal; a negative edge triggered state machine having a second input for receiving a second input signal and a second output for providing a second output signal; and a first combination logic coupled to the positive edge triggered state machine and the negative edge triggered state machine, the first combination logic having a third input for receiving third input signals and a third output for providing a third output signal, where (1) at least one of the first input signal and the second input signal includes an input clock signal having an input clock signal period, (2) the third input signals include the first output signal and the second output signal, and (3) the third output includes an output clock signal having an output clock signal period, where the output clock signal period is a multiple of the input clock signal period.
In one embodiment of the invention, the input to both the negative and positive edge triggered state machines is the input clock signal. Moreover, in one embodiment, the combination logic includes an AND gate.
In one embodiment of the invention, because the positive and negative edge triggered state machines change states only at the positive and negative transitions of the input clock signal, respectively, the positive and negative edge triggered state machines do not change states at the same time. This feature of the invention reduces the likelihood of glitches that result from simultaneous or substanially simultaneous changes in the states of state machines whose outputs are
The present invention is explained in more detail below with reference to the drawings.